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cy74fct2374t 8-bit register with 3-state outputs sccs040a ? september 1994 ? revised october 2001 1 post office box 655303 ? dallas, texas 75265 function and pinout compatible with fct and f logic 25- ? output series resistors to reduce transmission-line reflection noise reduced v oh (typically = 3.3 v) version of equivalent fct functions edge-rate control circuitry for significantly improved noise characteristics i off supports partial-power-down mode operation matched rise and fall times fully compatible with ttl input and output logic levels esd protection exceeds jesd 22 ? 2000-v human-body model (a114-a) ? 200-v machine model (a115-a) ? 1000-v charged-device model (c101) 3-state outputs 12-ma output sink current 15-ma output source current edge-triggered d-type inputs 250-mhz typical switching rate description the cy74fct2374t is a high-speed, low-power, octal d-type flip-flop featuring separate d-type inputs for each flip-flop. on-chip termination resistors at the outputs reduce system noise caused by reflections. the cy74fct2374t can replace the cy74fct374t to reduce noise in an existing design. the device has 3-state outputs for bus-oriented applications. a buffered clock (cp) and output-enable (oe ) inputs are common to all flip-flops. the flip-flops in the cy74fct2374t store the state of their individual data (d) inputs that meet the setup-time and hold-time requirements on the low-to-high cp transition. when oe is low, the contents of the flip-flops are available at the outputs. when oe is high, the outputs are in the high-impedance state. the state of oe does not affect the state of the flip-flops. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. copyright ? 2001, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 oe o 0 d 0 d 1 o 1 o 2 d 2 d 3 o 3 gnd v cc o 7 d 7 d 6 o 6 o 5 d 5 d 4 o 4 cp sn74fct2374t ...q or so p ackage (top view)
cy74fct2374t 8-bit register with 3-state outputs sccs040a ? september 1994 ? revised october 2001 2 post office box 655303 ? dallas, texas 75265 ordering information t a package ? speed (ns) orderable part number top-side marking qsop ? q tape and reel 5.2 cy74fct2374ctqct fct2374c soic so tube 5.2 cy74fct2374ctsoc fct2374c soic ? so tape and reel 5.2 cy74fct2374ctsoct fct2374c 40 cto85 c qsop ? q tape and reel 6.5 cy74fct2374atqct fct2374a ? 40 c to 85 c soic so tube 6.5 cy74fct2374atsoc fct2374a soic ? so tape and reel 6.5 cy74fct2374atsoct fct2374a soic so tube 10 cy74fct2374tsoc fct2374 soic ? so tape and reel 10 cy74fct2374tsoct fct2374 ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. function table inputs output d cp oe o h l h l ll x x h z h = high logic level, l = low logic level, x = don ? t care, z = high-impedance state, = low-to-high clock transition logic diagram (positive logic) cp d 1 11 oe cp d 0 o 0 to seven other channels 32 q
cy74fct2374t 8-bit register with 3-state outputs sccs040a ? september 1994 ? revised october 2001 3 post office box 655303 ? dallas, texas 75265 absolute maximum rating over operating free-air temperature range (unless otherwise noted) ? supply voltage range to ground potential ? 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc input voltage range ? 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc output voltage range ? 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc output current (maximum sink current/pin) 120 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 1): q package 68 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . so package 58 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ambient temperature range with power applied, t a ? 65 c to 135 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: the package thermal impedance is calculated in accordance with jesd 51-7. recommended operating conditions (see note 2) min nom max unit v cc supply voltage 4.75 5 5.25 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v i oh high-level output current ? 15 ma i ol low-level output current 12 ma t a operating free-air temperature ? 40 85 c note 2: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation.
cy74fct2374t 8-bit register with 3-state outputs sccs040a ? september 1994 ? revised october 2001 4 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ ? max unit v ik v cc = 4.75 v, i in = ? 18 ma ? 0.7 ? 1.2 v v oh v cc = 4.75 v, i oh = ? 15 ma 2.4 3.3 v v ol v cc = 4.75 v, i ol = 12 ma 0.3 0.55 v r out v cc = 4.75 v, i ol = 12 ma 20 25 40 ? v hys all inputs 0.2 v i i v cc = 5.25 v, v in = v cc 5 a i ih v cc = 5.25 v, v in = 2.7 v 1 a i il v cc = 5.25 v, v in = 0.5 v 1 a i ozh v cc = 5.25 v, v out = 2.7 v 10 a i ozl v cc = 5.25 v, v out = 0.5 v ? 10 a i os ? v cc = 5.25 v, v out = 0 v ? 60 ? 120 ? 225 ma i off v cc = 0 v, v out = 4.5 v 1 a i cc v cc = 5.25 v, v in 0.2 v, v in v cc ? 0.2 v 0.1 0.2 ma ? i cc v cc = 5.25 v, v in = 3.4 v , f 1 = 0, outputs open 0.5 2 ma i ccd ? v cc = 5.25 v, outputs open, one input switching at 50% duty cycle, oe = gnd, v in 0.2 v or v in v cc ? 0.2 v 0.06 0.12 ma/ mhz # v cc = 5 25 v one bit switching at f 1 = 5 mhz v in 0.2 v or v in v cc ? 0.2v 0.7 1.4 i c # v cc = 5 . 25 v , outputs open, 1 at 50% duty cycle v in = 3.4 v or gnd 1.2 3.4 ma i c # , f 0 = 10 mhz, oe = gnd eight bits switching at f 1 = 2.5 mhz v in 0.2 v or v in v cc ? 0.2 v 1.6 3.2 || ma 1 at 50% duty cycle v in = 3.4 v or gnd 3.9 12.2 || c i 5 10 pf c o 9 12 pf ? typical values are at v cc = 5 v, t a = 25 c. ? not more than one output should be shorted at a time. duration of short should not exceed one second. the use of high-speed tes t apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational valu es. otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parame tric tests. in any sequence of parameter tests, i os tests should be performed last. per ttl-driven input (v in = 3.4 v); all other inputs at v cc or gnd ? this parameter is derived for use in total power-supply calculations. # i c = i cc + ? i cc d h n t + i ccd (f 0 /2 + f 1 n 1 ) where: i c = total supply current i cc = power-supply current with cmos input levels ? i cc = power-supply current for a ttl high input (v in = 3.4 v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f 0 = clock frequency for registered devices, otherwise zero f 1 = input signal frequency n 1 = number of inputs changing at f 1 all currents are in milliamperes and all frequencies are in megahertz. || values for these conditions are examples of the i cc formula.
cy74fct2374t 8-bit register with 3-state outputs sccs040a ? september 1994 ? revised october 2001 5 post office box 655303 ? dallas, texas 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) cy74fct2374t cy74fct2374at cy74fct2374ct unit min max min max min max unit t w pulse duration, cp 7 5 4 ns t su setup time, data before cp 2 2 1.5 ns t h hold time, data after cp 1.5 1.5 1 ns switching characteristics over operating free-air temperature range (see figure 1) parameter from to cy74fct2374t cy74fct2374at cy74fct2374ct unit parameter (input) (output) min max min max min max unit t plh cp o 2 10 2 6.5 2 5.2 ns t phl cp o 2 10 2 6.5 2 5.2 ns t pzh oe o 1.5 12.5 1.5 6.5 1.5 6.2 ns t pzl oe o 1.5 12.5 1.5 6.5 1.5 6.2 ns t phz oe o 1.5 8 1.5 5.5 1.5 5 ns t plz oe o 1.5 8 1.5 5.5 1.5 5 ns
cy74fct2374t 8-bit register with 3-state outputs sccs040a ? september 1994 ? revised october 2001 6 post office box 655303 ? dallas, texas 75265 parameter measurement information 3 v 3 v 0 v 0 v t h t su voltage waveforms setup and hold times data input t plh t phl t phl t plh v oh v oh v ol v ol 3 v 0 v input out-of-phase output in-phase output timing input voltage waveforms propagation delay times inverting and noninverting outputs output control output waveform 1 (see note b) output waveform 2 (see note b) v ol v oh t pzl t pzh t plz t phz 3.5 v 0 v v ol + 0.3 v 0 v 3 v voltage waveforms enable and disable times low- and high-level enabling t plh /t phl t plz /t pzl t phz /t pzh open 7 v open test s1 3 v 0 v t w voltage waveforms pulse duration input notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. the outputs are measured one at a time with one input transition per measurement. from output under test c l = 50 pf (see note a) load circuit for 3-state outputs s1 7 v 500 ? gnd from output under test c l = 50 pf (see note a) test point load circuit for totem-pole outputs open v oh ? 0.3 v 500 ? 500 ? 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v figure 1. load circuit and voltage waveforms
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 74fct2374atsocte4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74FCT2374ATSOCTG4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74fct2374ctsocte4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74fct2374ctsoctg4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74fct2574atqcte4 active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year 74fct2574atsocte4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74fct2574atsoctg4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74fct2574ctsocte4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74fct2574ctsoctg4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374atqct active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year cy74fct2374atqcte4 active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year cy74fct2374atqctg4 active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year cy74fct2374atsoc active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374atsoce4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374atsocg4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374atsoct active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374ctqct active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year cy74fct2374ctqcte4 active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year cy74fct2374ctqctg4 active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year cy74fct2374ctsoc active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374ctsoce4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374ctsocg4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374ctsoct active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374tsoc active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374tsoce4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim package option addendum www.ti.com 24-may-2007 addendum-page 1
orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) cy74fct2374tsocg4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374tsoct active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374tsocte4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2374tsoctg4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574atqct active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year cy74fct2574atqctg4 active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year cy74fct2574atsoc active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574atsoce4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574atsocg4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574atsoct active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574ctqct active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year cy74fct2574ctqcte4 active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year cy74fct2574ctqctg4 active ssop/ qsop dbq 20 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year cy74fct2574ctsoc active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574ctsoce4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574ctsocg4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574ctsoct active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574tsoc active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574tsoce4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574tsocg4 active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574tsoct active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574tsocte4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cy74fct2574tsoctg4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. package option addendum www.ti.com 24-may-2007 addendum-page 2
obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 24-may-2007 addendum-page 3
tape and reel information package materials information www.ti.com 19-may-2007 pack materials-page 1
device package pins site reel diameter (mm) reel width (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant cy74fct2374atqct dbq 20 mla 330 16 6.5 9.0 2.1 8 16 q1 cy74fct2374atsoct dw 20 mla 330 24 10.8 13.0 2.7 12 24 q1 cy74fct2374ctqct dbq 20 mla 330 16 6.5 9.0 2.1 8 16 q1 cy74fct2374ctsoct dw 20 mla 330 24 10.8 13.0 2.7 12 24 q1 cy74fct2374tsoct dw 20 mla 330 24 10.8 13.0 2.7 12 24 q1 cy74fct2574atqct dbq 20 mla 330 16 6.5 9.0 2.1 8 16 q1 cy74fct2574atsoct dw 20 mla 330 24 10.8 13.0 2.7 12 24 q1 cy74fct2574ctqct dbq 20 mla 330 16 6.5 9.0 2.1 8 16 q1 cy74fct2574ctsoct dw 20 mla 330 24 10.8 13.0 2.7 12 24 q1 cy74fct2574tsoct dw 20 mla 330 24 10.8 13.0 2.7 12 24 q1 tape and reel box information device package pins site length (mm) width (mm) height (mm) cy74fct2374atqct dbq 20 mla 0.0 0.0 0.0 cy74fct2374atsoct dw 20 mla 333.2 333.2 31.75 cy74fct2374ctqct dbq 20 mla 0.0 0.0 0.0 cy74fct2374ctsoct dw 20 mla 333.2 333.2 31.75 cy74fct2374tsoct dw 20 mla 333.2 333.2 31.75 cy74fct2574atqct dbq 20 mla 0.0 0.0 0.0 cy74fct2574atsoct dw 20 mla 333.2 333.2 31.75 cy74fct2574ctqct dbq 20 mla 0.0 0.0 0.0 cy74fct2574ctsoct dw 20 mla 333.2 333.2 31.75 cy74fct2574tsoct dw 20 mla 333.2 333.2 31.75 package materials information www.ti.com 19-may-2007 pack materials-page 2
package materials information www.ti.com 19-may-2007 pack materials-page 3

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